1. Field of the Invention
The present invention relates to a display device including a liquid crystal display (LCD) device, and more particularly, to a TFT array substrate and method for fabricating the same.
2. Discussion of the Related Art
Recently, liquid crystal display (LCD) devices have received much attention as flat panel display devices. The LCD devices have been actively studied owing to their high contrast ratio, suitability for displaying gray levels or moving pictures, and low power consumption.
Particularly, since LCD devices can be fabricated with a thin thickness, they can be used as a ultra slim display device such as wall-mountable TVs. Also, since LCD devices are lightweight and have a lower power consumption than CRTs, they are used as displays for notebook computers operating with batteries, personal portable terminals, TVs, and monitors for spacecrafts. In this way, LCD devices have received much attention as a display device for the next generation.
Generally, an LCD device includes a TFT array substrate provided with a TFT, a pixel electrode, and a storage capacitor in each pixel region defined by gate and data lines, a color filter array substrate provided with a color filter layer and a common electrode, and a liquid crystal layer interposed between the two substrates. The LCD device displays a picture image by applying a voltage to the electrodes to rearrange the liquid crystal molecules of the liquid crystal layer and controlling the light transmittance.
In such an LCD device, the TFT is used as a switching device for displaying images.
The TFT is formed at a crossing portion between the gate and data lines in a unit pixel region, and serves to switch a current with respect to the unit pixel region. During the on-state of the TFT, the current flows to charge a capacitor connected to a specific unit pixel region at a desired voltage. During the off-state, the charged state is maintained until the next period that the unit pixel region is addressed.
A voltage level determines a gray level that represents an amount of light transmitted through a liquid crystal layer corresponding to the unit pixel region.
The aforementioned TFT has two types of structures, i.e., a coplanar type TFT of which source and gate electrodes are arranged on one plane, and a staggered type TFT of which source and gate electrodes are arranged on different planes. In general, a polycrystalline silicon TFT employs the coplanar type TFT while an amorphous silicon TFT employs the staggered type TFT.
The staggered type TFT is divided into an inverted staggered type TFT and a normal staggered type TFT, wherein the inverted staggered type TFT includes a gate electrode arranged below source and drain electrodes, and the normal staggered type TFT includes a gate electrode arranged above source and drain electrodes. The inverted staggered type TFT is referred to as a bottom-gate type TFT, and the normal staggered type TFT is referred to as a top-gate type TFT.
Generally, the LCD device is provided with a bottom-gate type TFT. As shown by FIG. 1, the bottom-gate type TFT includes a gate electrode 12a, a gate insulating layer 13 provided on an entire surface including the gate electrode, a semiconductor (a-Si) layer 14 formed on the gate insulating layer on the gate electrode, an ohmic contact layer (n+a-Si) 14a provided in other regions except a channel region of the semiconductor layer, and source and drain electrodes 15a and 15b formed on the ohmic contact layer.
The gate insulating layer 13 is formed in such a manner that an inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx) having a dielectric constant of about 7.5 is deposited by a plasma enhanced chemical vapor deposition (PECVD) process.
However, when the gate insulating layer is formed by depositing such an inorganic material, the following problems may occur.
In other words, when the gate insulating layer is formed of such an inorganic material, it is difficult for the gate insulating layer to have a uniform thickness with a single deposition process. Accordingly, the deposition process should be performed twice. This complicates the fabrication process and increases the production costs.
To solve the above problem, a method for forming a gate insulating layer of an organic material having a dielectric constant of 3 to 4 has been suggested. By this method, the gate insulating layer can be formed by a simple process with inexpensive equipment.
Unlike the inorganic gate insulating layer, because the organic gate insulating layer is formed by a coating process, such as a spin coating or slit coating, not the PECVD process, the process steps are simplified and the production cost is reduced. Also, the steps of the gate line and the gate electrode is planarized by a uniform thickness of such an organic gate insulating layer.
However, because the organic gate insulating layer has a smaller dielectric constant than that of the inorganic gate insulating layer, when the organic and inorganic gate insulating layers have the same thickness, a parasitic capacitance (Cgs) value formed between a gate line layer and a data line layer becomes small. This is because an insulating layer formed between opposing electrodes has a capacitance value proportional to its dielectric constant and thickness, but inversely proportional to areas of the opposing electrodes.
If the parasitic capacitance (Cgs) value becomes small, voltage drop ΔVp increased as expressed by the following equation 1. Such a small parasitic capacitance (Cgs) value causes undesired effects such as a flicker, image sticking or uneven screen brightness.
                              Δ          ⁢                                          ⁢          Vp                =                              Cgs                          Cgs              +              Cst              +              Clc                                ⁢          Δ          ⁢                                          ⁢          Vg                                    [                  Equation          ⁢                                          ⁢          1                ]            
In this case, Cgs is parasitic capacitance formed between the gate electrode and the source and drain electrodes, Clc is capacitance accumulated in a liquid crystal cell, and Cst is capacitance formed in a storage capacitor. ΔVp is a differential voltage between a data voltage Vd applied to the source electrode and a voltage Vlc charged in the liquid crystal cell, and ΔVg is a differential voltage between a gate voltage Vgh of a high level and a gate voltage Vgl of a low level.
In other words, the parasitic capacitance Cgs greatly affects ΔVp as expressed by the equation 1, and is closely related to panel characteristics and picture quality characteristics. To lower ΔVp, the parasitic capacitance Cgs value should be increased. To increase the parasitic capacitance Cgs value, the dielectric constant of the gate insulating layer should be increased. Accordingly, the gate insulating layer should have a high dielectric constant.
As described above, the aforementioned related art method for fabricating the TFT array substrate has the following problems.
When an inorganic insulating layer of silicon nitride or silicon oxide is used for the gate insulating layer, the fabrication process becomes complicated and the production costs increase. Also, when an organic insulating layer such as PVA (polyvinyl alcohol) and PVP (polyvinyl phenol) is used for the gate insulating layer, ΔVp value increases due to the low dielectric constant of the organic insulating layer and the coating thickness of the gate insulating layer becomes uneven.
To solve the problems of the related art organic/inorganic insulating layer, a sol-gel type composite material has been recently suggested for the gate insulating layer.
Such a sol-gel type composite material is formed by chemically reacting silicon alkoxide with metal alkoxide. Then, the sol-gel composite material is mixed with a solvent, uniformly coated on a substrate, soft-baked at a temperature of 70° C., and hard-baked at a temperature of 300° to form the gate insulating layer.
However, a crack may occur on the surface of the gate insulating layer during the soft-baking and hard-baking processes.